A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform
نویسندگان
چکیده
A lifting based 2D DWT with efficient folded architecture and parallel scanning is being proposed. The architecture results in lesser hardware complexity and memory requirement due to multiplexing of 2 stages of lifting architecture. The 2D DWT architecture is realized by cascading two 2D processing elements. The coefficients for the lifting stage were chosen according with 9/7 filter. The 1D processing element has a column filter, transposing buffer and a row filter in it. The use of parallel scanning reduces the size of transposing buffer. Combining the intermediate results of row and column, the number of pipelining stages and registers are also reduced. The throughput obtained are 2 input and 2 output per cycle. The critical path for proposed architecture is one Tm.
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